View AR0331SRSC00SHCAH-GEVB_8251241.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ar0331: 1/3-inch 3.1 mp/full hd digital image sensor features ar0331_ds rev. l pub. 5/15 en 1 ?semiconductor components industries, llc 2015, 1/3-inch 3.1 mp/full hd digital image sensor ar0331 datasheet, rev. l for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance ? latest 2.2 ? m pixel with on semiconductor a-pix? technology ? full hd support at 1080p 60 fps for superior video performance ? linear or high dynamic range capture ? 3.1m (4:3)and 1080p full hd (16:9) images ? optional adaptive local tone mapping (altm) ? interleaved t1/t2 output ? support for external mechanical shutter ? support for external led or xenon flash ? slow-motion video (vga 120 fps) ? on-chip phase-locked loop (pll) oscillator ? integrated position-based color and lens shading correction ? slave mode for precise frame-rate control ? stereo/3d camera support ? statistics engine ? data interfaces: four-lane serial high-speed pixel interface (hispi?) differential signaling (slvs and hiv cm ), or parallel ? auto black level calibration ? high-speed context switching ?temperature sensor applications ? video surveillance ? stereo vision ?smart vision ?automation ?machine vision ? 1080p60 video applications ? high dynamic range imaging general description the on semiconductor ar0331 is a 1/3-inch cmos digital image sensor with an active-pixel array of 2048hx1536v. it captures images in either linear or high dynamic range modes, with a rolling-shutter readout. it includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. it is designed for both low light and high dynamic range scene performance. it is programmable through a simple two-wire serial inter- face. the ar0331 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continu- ous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. table 1: key parameters parameter typical value optical format 1/3-inch (5.8 mm) note: sensor optical format will also work with lenses designed for 1/3.2 format. active pixels 2048(h) x 1536(v) (4:3, mode) pixel size 2.2 ? m x 2.2 ?? m color filter array rgb bayer shutter type electronic rolling shutter and grr input clock range 6 C 48 mhz output clock maximum 148.5 mp/s (4-lane hispi) 74.25 mp/s (parallel) output serial hispi 10-, 12-, 14-, or 16-bit parallel 10-, 12-bit frame rate full resolution 30 fps 1080p 60 fps responsivity 1.9 v/lux-sec snr max 39 db max dynamic range up to 100 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3v - 0.6v, 1.7 v - 1.9 v power consumption (typical) <780 mw operating temperature (ambient) C30c to + 85 c package options 10 x 10 mm 48 pin ilcc 9.5 x 9.5 mm 63-pin ibga
ar0331_ds rev. l pub. 5/15 en 2 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description ar0331srsc00shca0-drbr 48-pin ilcc hispi, 0 cra dry pa ck without protective film, double side bbar glass ar0331srsc00shcad3-gevk 48-pin ilcc hispi, 0 cra demo kit 3 ar0331srsc00shcad-gevk 48-pin ilcc hispi, 0 cra demo kit AR0331SRSC00SHCAH-GEVB 48-pin ilcc hispi, 0 cra demo board ar0331srsc00suca0-dpbr 48-pin ilcc parallel, 0 cra dry pack with protective film, double side bbar glass ar0331srsc00suca0-drbr 48-pin ilcc parallel, 0 cra dry pa ck without protective film, double side bbar glass ar0331srsc00sucad3-gevk 48-pin ilcc parallel, 0 cra demo kit 3 ar0331srsc00sucad-gevk 48-pin ilcc parallel, 0 cra demo kit ar0331srsc00sucah-gevb 48-pin ilcc parallel, 0 cra demo board ar0331srsc00xuead3-gevk 63-pin ibga demo kit 3 ar0331srsc00xuead-gevk 63-pin ibga demo kit ar0331srsc00xueah-gevb 63-pin ibga demo board ar0331srsc00xuee0-by-drbr 63-pin ibga, 0 cra 0 dry pack without protective film, double side bbar glass ar0331srsc00xuee0-dpbr 63-pin ibga, 0 cra 0 dry pack with protective film, double side bbar glass ar0331srsc00xuee0-drbr 63-pin ibga, 0 cra 0 dry pack without protective film, double side bbar glass ar0331srsc00xuee0-drbr1 63-pin ibga, 0 cra 0 dry pack without protective film, double side bbar glass
ar0331_ds rev. l pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor ordering information
ar0331_ds rev. l pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 pixel output interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 pixel sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 gain stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 pedestals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 high dynamic range mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 sensor pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 sensor readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 sensor frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 frame readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 changing sensor modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ar0331_ds rev. l pub. 5/15 en 4 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 48 ilcc package, parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 48 ilcc package, hispi output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: 9.5 x 9.5 mm 63-ball ibga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 9: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 10: hispi transmitter and receiver interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 11: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: block diagram of dll timing ad justment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 13: delaying the clock with respect to data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14: delaying data with respect to the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: integration control in ers readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 16: example of 8.33ms integration in 16.6ms frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: the row integration time is grea ter than the frame readout ti me . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: gain stages in ar0331 sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: hdr data compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 20: pll dividers affecting vco freq uency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 21: sensor dual readout paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 22: pll for the parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23: pll for the serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 24: effect of horizontal mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 25: effect of vertical flip on re adout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 26: horizontal binning in the ar0331 sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 27: vertical row binning in the ar033 1 sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 28: frame period measured in clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 29: slave mode active state and vert ical blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 30: slave mode example with equal integration and fram e readout periods . . . . . . . . . . . . . . . . . . . . . .38 figure 31: slave mode example where the integration period is half of the frame readout period . . . . . . . . .39 figure 32: example of the sensor output of a 1928 x 1088 frame at 60 fps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 33: example of the sensor output of a 1928 x1088 frame at 30 fps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 34: example of changing the sensor from context a to co ntext b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 35: frame format with em bedded data lines enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 36: format of embedded statistics ou tput within a frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 37: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 38: single read fr om current location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 39: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 40: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 41: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 42: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 43: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 44: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 45: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 46: power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 47: power down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 48: 48 ilcc parallel package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 49: 48 ilcc hispi package outline draw ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 50: 63-ball ibga package outline dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ar0331_ds rev. l pub. 5/15 en 5 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor list of tables list of tables table 1: key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: pin descriptions, 48 ilcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: pin descriptions, 9.5 x 9.5 mm, 63-ball ibga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: output enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7: configuration of the pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 8: recommended sensor gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 9: companding table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 10: knee points for compression from 16 bits to 12 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 11: bit operation after linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 12: pll parameters for the parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 13: example pll configuration for the parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 14: pll parameters for the serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 15: example pll configurations for the serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 16: minimum vertical blanking configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 17: serial sync codes incl uded with each protocol included with th e ar0331 sensor . . . . . . . . . . . . . .40 table 18: list of configurable registers for context a and contex t b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 19: a-law compression table for 12-10 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 20: test pattern modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 21: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 22: i/o timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 23: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 24: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 25: operating current consumption in pa rallel output and linear mode . . . . . . . . . . . . . . . . . . . . . . . . .58 table 26: operating current consumption in pa rallel output and hdr mode . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 27: operating current in hispi (hivcm) output and linear mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 28: operating current in hispi (hivcm) output and hdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 29: operating current in hispi (slvs) output and linear mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 30: operating current in hispi (slvs) output and hdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 31: channel skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 32: clock dll steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 33: data dll steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 34: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 35: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
ar0331_ds rev. l pub. 5/15 en 6 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor general description general description the on semiconductor ar0331 can be operated in its default mode or programmed for frame size, exposure, gain, and other parame ters. the default mode output is a 1080p- resolution image at 60 frames per second (fps). in linear mode, it outputs 12-bit or 10-bit a-law compressed raw data, using either the pa rallel or serial (hispi) output ports. in high dynamic range mode, it outputs 12-bit compressed data using parallel output. in hispi mode, 12- or 14-bit compressed, or 16-bit linearized data may be output. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0331 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. the sensor is designed to operate in a wide temperature range (?30c to +85c). functional overview the ar0331 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1: block diagram row noise correction black level correction adaptive cd filter motion correction and blue halo filter hdr linearization (me or dlo) pixel defect correction smooting filter digital gain and pedestal 12 12 16 companding 16, 14, or 12 bits parallel hispi 12 b its ( hdr and linear), 12 or 10 bits linear test pattern generator adc data
ar0331_ds rev. l pub. 5/15 en 7 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 3.1 mp active- pi xel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correc tion and gain), and then through an analog- to-digital converter (adc). th e output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and appl ies digital gain). the sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 16-bit per pixel value. a compression mode is further offered to allow the 16-bit pixel value to be transmitte d to the host system as a 12-bit value with close to zero loss in image quality. figure 2: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the parallel interface output pads can be left un connected if the serial output interface is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C48 mhz) s data sclk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2 analog power 1 v aa _pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n v dd _slvs trigger oe_bar s addr shutter flash
ar0331_ds rev. l pub. 5/15 en 8 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview out and design considerations. refer to the ar0 331 demo headboard schema tics for circuit recom- mendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. figure 3: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the serial interface output pads and v dd slvs can be left unconnected if the parallel output inter- face is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. refer to the ar0 331 demo headboard schema tics for circuit recom- mendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the extclk input is limited to 6-48 mhz. v dd master clock (6-48 mhz) s data sclk test frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, v aa v aa _pix analog power 1 vdd_pll pll power 1 analog power 1 v aa _pix v dd _io v dd _pll v dd v aa trigger oe_bar a gnd s addr shutter flash
ar0331_ds rev. l pub. 5/15 en 9 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview figure 4: 48 ilcc package, parallel output 6 5 4 3 2 1 48 47 46 45 44 43 d gnd extclk v dd _p ll d out 6 d gnd nc 7 d out 7 nc 42 8 d out 8 nc 41 9 d out 9 v aa 40 10 d out 10 a gnd 39 11 d out 11 v aa _p ix 38 12 v dd _io v aa _p ix 37 13 pixclk v aa 36 14 v dd a gnd 35 15 s clk v aa 34 16 s data reserved 33 17 reset_bar nc 32 18 v dd _io reserved 31 v dd nc nc nc s addr test flash trigger frame_valid line_valid d gnd 19 20 21 22 23 24 25 26 27 28 29 30 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 oe_bar
ar0331_ds rev. l pub. 5/15 en 10 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview table 1: pin descriptions pin number name type description 1d out 4 output parallel pixel data output. 2d out 5 output parallel pixel data output. 3d out 6 output parallel pixel data output. 4v dd _pll power pll power. 5 extclk input external input clock. 6d gnd power digital ground. 7d out 7 output parallel pixel data output. 8d out 8 output parallel pixel data output. 9d out 9 output parallel pixel data output. 10 d out 10 output parallel pixel data output. 11 d out 11 output parallel pixel data output (msb). 12 v dd _io power i/o supply power. 13 pixclk output pixel clock out. d out is valid on rising edge of this clock. 14 v dd power digital power. 15 s clk input two-wire serial clock input. 16 s data i/o two-wire serial data i/o. 17 reset_bar input asynchronous reset (active lo w). all settings are restored to factory default. 18 v dd _io power i/o supply power. 19 v dd power digital power. 20 nc 21 nc 22 nc 23 oe_bar input output enable (active low). 24 s addr input two-wire serial address select. 0: 0x20. 1: 0x30 25 test input manufacturing test enable pin (connect to d gnd ). 26 flash output flash output control. 27 trigger input receives slave mode vd signal for frame rate synchronization and trigger to start a grr frame. 28 frame_valid output asserted when d out frame data is valid. 29 line_valid output asserted when d out line data is valid. 30 d gnd power digital ground 31 reserved 32 shutter output control for external mechanical s hutter. can be left floating if not used. 33 reserved 34 v aa power analog power. 35 a gnd power analog ground. 36 v aa power analog power. 37 v aa _pix power pixel power. 38 v aa _pix power pixel power. 39 a gnd power analog ground. 40 v aa power analog power. 41 nc
ar0331_ds rev. l pub. 5/15 en 11 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview figure 5: 48 ilcc package, hispi output 42 nc 43 nc 44 d gnd power digital ground. 45 d out 0 output parallel pixel data output (lsb) 46 d out 1 output parallel pixel data output. 47 d out 2 output parallel pixel data output. 48 d out 3 output parallel pixel data output. table 1: pin descriptions (continued) pin number name type description 654321484746454443 d gnd slvs0_n slvs0_p slvs1_n slvs3_p nc 7 nc 42 8 nc 41 9 d gnd v aa 40 10 a gnd 39 11 v aa _p ix 38 12 v dd _io v aa _p ix 37 13 extc lk v aa 36 14 v dd a gnd 35 15 s clk v aa 34 16 s data 33 17 reset_bar shutter 32 18 v dd _io reserved 31 v dd nc nc s addr flash trigger d gnd 19 20 21 22 23 24 25 26 27 28 29 30 slvs1_p slvsc_n slvsc_p slvs2_n slvs2_p slvs3_n oe_bar v dd v dd _slvs d gnd test d gnd v dd _io v dd _pll reserved nc
ar0331_ds rev. l pub. 5/15 en 12 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview table 2: pin descriptions, 48 ilcc pin number name type description 1 slvsc_n output hispi serial ddr clock differential n. 2 slvs1_p output hispi serial data, lane 1, differential p. 3 slvs1_n output hispi serial data, lane 1, differential n. 4 slvs0_p output hispi serial data, lane 0, differential p. 5 slvs0_n output hispi serial data, lane 0, differential n. 6nc 7v dd _slvs power 0.3v-0.6v or 1.7v - 1.9v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring v dd _slvs to 1.7 C 1.9v. 8v dd _io power i/o supply power. 9d gnd power digital ground. 10 v dd power digital power. 11 extclk input external input clock. 12 v dd power digital power. 13 d gnd digital ground. 14 v dd _io power i/o supply power. 15 s data i/o two-wire serial data i/o. 16 s clk input two-wire serial clock input. 17 test manufacturing test enable pin (connect to d gnd ). 18 reset_bar input asynchronous reset (active low). all settings are restored to factory default. 19 v dd power digital power. 20 d gnd power digital ground. 21 v dd _io power i/o supply power. 22 nc 23 s addr input two-wire serial address select. 0: 0x20. 1: 0x30 24 nc 25 oe_bar output enable (active low). 26 trigger input receives slave mode vd signal for frame rate synchronization and trigger to start a grr frame. 27 flash output flash output control. 28 d gnd power 29 v dd _pll power pll power. 30 reserved 31 a gnd power analog ground. 32 v aa power analog power. 33 reserved 34 shutter output control for external mechanical shutter. can be left floating if not used. 35 v aa _pix power pixel power. 36 v aa _pix power pixel power. 37 nc 38 v aa power analog power. 39 nc 40 nc
ar0331_ds rev. l pub. 5/15 en 13 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview figure 6: 9.5 x 9.5 mm 63-ball ibga package 41 v aa power analog power. 42 a gnd power analog ground. 43 d gnd power digital ground. 44 slvs3_p output hispi serial data, lane 3, differential p. 45 slvs3_n output hispi serial data, lane 3, differential n. 46 slvs2_p output hispi serial data, lane 2, differential p. 47 slvs2_n output hispi serial data, lane 2, differential n 48 slvsc_p output hispi serial ddr clock differential p. table 2: pin descriptions, 48 ilcc (continued) pin number name type description a b c d e f g h top view (ball down) slvs0_n slvs0_p slvs1_n slvs1_p v dd nc v dd _pll slvs_cn slvsc_p slvs2_n slvs2_p v dd v aa v aa extclk v dd _ slvs slvs3_n slvs3_p d gnd v dd a gnd s addr s clk s data d gnd d gnd v dd v aa _pix v aa _pix line_ valid frame_ valid pixclk flash d gnd v dd _io nc d out 8 d out 9d out 10 d out 11 d gnd v dd _io test d out 4d out 5d out 6d out 7d gnd v dd _io trigger oe_bar d out 0d out 1d out 2d out 3d gnd v dd _io v dd _io reset_ bar 12 3 567 8 4 v dd a gnd shutter reserved (nc)
ar0331_ds rev. l pub. 5/15 en 14 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview table 3: pin descriptions, 9.5 x 9.5 mm, 63-ball ibga name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n. slvs0_p a3 output hispi serial data, lane 0, differential p. slvs1_n a4 output hispi serial data, lane 1, differential n. slvs1_p a5 output hispi serial data, lane 1, differential p. v dd _pll b1 power pll power. slvsc_n b2 output hispi serial ddr clock differential n. slvsc_p b3 output hispi serial ddr clock differential p. slvs2_n b4 output hispi serial data, lane 2, differential n. slvs2_p b5 output hispi serial data, lane 2, differential p. v aa b7, b8 power analog power. extclk c1 input external input clock. v dd _slvs c2 power 0.3v-0.6v or 1.7v - 1.9v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring v dd _slvs to 1.7 C 1.9v. slvs3_n c3 output hispi serial data, lane 3, differential n. slvs3_p c4 output hispi serial data, lane 3, differential p. d gnd c5, d4, d5, e5, f5, g5, h5 power digital ground. v dd a6, a7, b6, c6, d6 power digital power. a gnd c7, c8 power analog ground. s addr d1 input two-wire serial address select. 0: 0x20. 1: 0x30 s clk d2 input two-wire serial clock input. s data d3 i/o two-wire serial data i/o. v aa _pix d7, d8 power pixel power. line_valid e1 output asserted when d out line data is valid. frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. v dd _io e6, f6, g6, h6, h7 power i/o supply power. d out 8 f1 output parallel pixel data output. d out 9 f2 output parallel pixel data output. d out 10 f3 output parallel pixel data output. d out 11 f4 output parallel pixel data output (msb) test f7 input. manufacturing test enable pin (connect to d gnd ). d out 4 g1 output parallel pixel data output. d out 5 g2 output parallel pixel data output. d out 6 g3 output parallel pixel data output. d out 7 g4 output parallel pixel data output. trigger g7 input exposure synchronization input. oe_bar g8 input output enable (active low). d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output. d out 2 h3 output parallel pixel data output. d out 3 h4 output parallel pixel data output.
ar0331_ds rev. l pub. 5/15 en 15 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor functional overview reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default. shutter e8 output control for external mechanical shutter. can be left floating if not used. flash e4 output flash control output. nc a8, e7 reserved f8 table 3: pin descriptions, 9.5 x 9.5 mm, 63-ball ibga (continued) name ibga pin type description
ar0331_ds rev. l pub. 5/15 en 16 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel data format pixel data format pixel array structure while the sensor's format is 2048x1536, addi tional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for mono- chrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity wi thin the active area. not all dummy pixels or barrier pixels can be read out. figure 7: pixel array description notes: 1. maximum of 2048 columns is supported. addi tional columns included for mirroring operations. 16 b arr i er + 4 b or d er p i xe l s light dummy pixel active pixel 18 barrier + 4 border pixels 2064 2 barrier + 4 border pixels 2 barrier + 4 border pixels 1578 2052 1 x 1536 4.51mm x 3.38 mm
ar0331_ds rev. l pub. 5/15 en 17 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel data format figure 8: pixel color pattern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 8). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (0, 0). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 9. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced as shown in figure 9. figure 9: imaging a scene active pixel (0,0) array pixel (0, 0) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction lens pixel (0,0) row readout order column readout order scene sensor (rear view)
ar0331_ds rev. l pub. 5/15 en 18 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel output interfaces pixel output interfaces parallel interface the parallel pixel data interfac e uses these output-only signals: ?frame_valid ?line_valid ?pixclk ?d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. table 5 shows the recommended settings. when the parallel pixel data interface is in us e, the serial data output signals can be left unconnected. set reset_register [bit 12 (r0x301a [12] = 1)] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is en abled, its signals can be switched asynchro- nously between the driven and high-z under pin or register control, as shown in table 4. configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 5. high speed serial pixel data interface the high speed serial pixel (hispi) interface uses four data lanes and one clock as output. ?slvsc_p ?slvsc_n ?slvs0_p ?slvs0_n ?slvs1_p ?slvs1_n table 4: output enable control oe_bar pin drive pins r0x301a[6] description 1 0 interface high-z x1interfacedriven 0xinterfacedriven table 5: configuration of the pixel data interface serializer disable r0x301 a[12] parallel enable r0x301 a[7] description 0 0 power up default. serial pixel data interface and its clocks are enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.
ar0331_ds rev. l pub. 5/15 en 19 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel output interfaces ?slvs2_p ?slvs2_n ?slvs3_p ?slvs3_n the hispi interface supports three protocols, streaming-s, streaming-sp, and packetized sp. the streaming protocols conform to a stan dard video application where each line of active or intra-frame bl anking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. these protocols are further described in the high-speed serial pixel (hispi?) interface protocol specification v1.50.00. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 10 shows the configuration between the hispi transmitter and the receiver. figure 10: hispi transmitter and receiver interface block diagram hispi physical layer the hispi physical layer is partitioned into bl ocks of four data lanes and an associated clock lane. any reference to the phy in the remainder of this document is referring to this minimum building block. the phy will serialize 10-, 12-, 14-, or 16-bit data words and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of the clock. figure 11 shows bit transmission. in this example, the word is transmitted in order of msb to lsb. the receiver latches data at the rising and falling edge of the clock. a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0
ar0331_ds rev. l pub. 5/15 en 20 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel output interfaces figure 11: timing diagram dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa- tion. figure 12: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay delay delay delay delay data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 clock_del[2:0] data0_del[2:0] data1_del[2:0] data2_del[2:0] data3_del[2:0]
ar0331_ds rev. l pub. 5/15 en 21 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel output interfaces figure 13: delaying the clock with respect to data figure 14: delaying data with respect to the clock hispi protocol layer the hispi protocol is described the hi spi protocol specification document. datan (datan_del = 000) cp (clock_del = 000) cp (clock_del = 001) cp (clock_del = 010) cp (clock_del = 011) cp (clock_del = 100) cp (clock_del = 101) c p (clock_del = 110) cp (clock_del =111) increasing clock_del [2:0] increases clock delay 1 ui 1 ui t dllstep cp ( clock_del = 000) datan (datan_del = 000) datan(datan_del = 001) datan(datan_del = 010) datan(datan_del = 011) datan(datan_del = 100) datan(datan_del = 101) datan(datan_del = 110) datan(datan_del = 111) increasing datan_del [2:0] increases data delay
ar0331_ds rev. l pub. 5/15 en 22 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pixel sensitivity serial configuration the serial format should be configured us ing r0x31ac. refer to the ar0331 register reference document for more detail regarding this register. the serial_format register (r0x31ae) controls which serial format is in use when the serial interface is enabled (reset_register[12] = 0). the following serial formats are supported: ? 0x0304 - sensor supports quad-lane hispi operation ? 0x0302 - sensor supports dual-lane hispi operation ? 0x0301 - sensor supports single-lane hispi operation pixel sensitivity figure 15: integration control in ers readout a pixel's integration time is defined by the number of clock periods between a row's reset and read operation. both the read followed by the reset operations occur within a row period (t row ) where the read and reset may be applied to different rows. the read and reset operations will be applied to the ro ws of the pixel array in a consecutive order. the coarse integration time is defined by the number of row periods (t row ) between a row's reset and the row read. the row period is defined as the ti me between row read operations (see sensor frame rate). t coarse = t row * coarse_integration_time (eq 1) row integration (t integration ) row reset (start of integration) row readout
ar0331_ds rev. l pub. 5/15 en 23 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor gain stages figure 16: example of 8.33ms integration in 16.6ms frame figure 17: the row integration time is greater than the frame readout time the minimum frame-time is defined by the number of row periods per frame and the row period. the sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines . gain stages the analog gain stages of the ar0331 sensor are shown in figure 18. the sensor analog gain stage consists of a variable adc refere nce. the sensor will apply the same analog gain to each color channel. digital gain can be configured to separate levels for each color channel. vertical blanking read reset vertical blanking horizontal blanking t frame = frame_length_lines x t row 16.6 ms = 750 rows x 22.22 s/row t coarse = coarse_integration_time x t row 8.33 ms =563 rows x 22.22 s/row time image vertical blanking horizontal blanking vertical blanking t frame = frame_length_lines * t row 16.6ms = 1125 rows *14.8us/row shutter pointer read pointer t coarse = coarse_integration_time* t row 20.7ms = 1390 rows *14.8us/row time extended vertical blanking image horizontal blanking 4.1ms
ar0331_ds rev. l pub. 5/15 en 24 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor gain stages figure 18: gain st ages in ar0331 sensor the level of analog gain applied is controlled by the coarse_gain register. the recom- mended analog gain settings are listed in table 6. a minimum analog gain of 1.23x is recommended. changes to these registers sh ould be done prior to streaming images. each digital gain can be configured from a gain of 0 to 15.992. the digital gain supports 128 gain steps per 6db of gain. the format of each digital gain regi ster is ?xxxx.yyyyyyy? where ?xxxx? refers an integer gain of 1 to 15 and ?yyyyyyy? is a fractional gain ranging from 0/128 to 127/128. the sensor includes a digital dithering feat ure to reduce quantization noise resulting from using digital gain. it can be disabled by setting r0x30ba[5] to 0. the default value is 1. table 6: recommended sensor gain coarse_gain (0x3060[5:4])/ coarse_gain_cb (0x3060[13:12]) fine_gain (0x3060[3:0])/ fine_gain_cb (0x3060[11:8]) adc gain 0 6 1.23 0 7 1.28 0 8 1.34 0 9 1.39 0101.45 0111.52 0121.60 0131.69 0141.78 0151.88 1 0 2.00 1 2 2.14 1 4 2.28 1 6 2.47 1 8 2.67 1102.91 1123.20 1143.56 204 2 4 4.56 2 8 5.34 2126.41 308 adc reference digital gain with dithering 1x, 2x, 4x, and 8x 1x to 16x (128 steps per 6db)
ar0331_ds rev. l pub. 5/15 en 25 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor pedestals pedestals there are two types of constant offset pedestals that may be adjusted at the end of the datapath. the data pedestal is a constant offset that is added to pixel values at the end of the data- path. the default offset when altm is disabled is 168 and is a 12-bit offset. this offset matches the maximum range used by the corrections in the digital readout path. the purpose of the data pedestal is to convert ne gative values generated by the digital data- path into positive output data. it is reco mmended that the data pedestal be set to 16 when altm is enabled. the data pedestal value can be changed from its default value by adjusting register r0x301e. the altm pedestal (r0x2450) is also located at the end of the datapath. the altm pedestal default offset is 0. high dynamic range mode by default, the sensor powers up in hdr mode. the hdr scheme used is multi-exposure hdr. this allows the sensor to handle up to 100db of dynamic range. in hdr mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the roll ing shutter readout. the intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. as soon as a pixel's two exposure values ar e available, they are combined to create a linearized 16-bit value for each pixel?s response. depending on whether hispi or parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using adaptive local tone mapping (alt m), or companded to 12 or 14 bits. adaptive local tone mapping real- world scenes often have a very high dynamic range (hdr) that far exceeds the electrical dynamic range of the imager. dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. even though the ar0331 can capture full dynamic range images, the images are still limited by the low dynamic range of display devices. today?s typical lcd moni tor has a contrast ratio around 1,000:1 while it is not atypical for an hdr image having a contrast ratio of around 250,000:1. there- fore, in order to reproduce hdr images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. this is commonly called tone ma pping. the ar0331 has implemented an adap- tive local tone mapping (altm) feature to reproduce visually a ppealing images that increase the local contrast and the visibility of the images. when altm is enabled, the gamma in the backend isp should be set to 1 for proper display. see the ar0331 devel- oper guide for more information on altm.
ar0331_ds rev. l pub. 5/15 en 26 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor high dynamic range mode companding the 16-bit linearized hdr image may be compressed to 12 bits using on-chip companding. figure 19 illustrates the compress ion from 16- to 12-bits. companding is enabled by setting r0x31d0. table 8 shows the knee points for the different modes. figure 19: hdr data compression table 9 illustrates the input and output code s as well as compandi ng and decompanding formulas for each of the four colored segments in figure 19. table 7: companding table segment 1 segment 2 segment 3 segment 4 input code range 0 to 1023 1024 to 4095 4096 to 32767 32768 to 65535 output code range 0 to 1023 1024 to 2559 2560 to 3455 3456 to 3967 companding formula p out = p in p out = (p in - 1024)/2 + 1024 p out = (p in - 4096)/32 + 2560 p out = (p in - 32768)/64 + 3456 decompanding formula p out = p in p out = (p in - 1024)*2 + 1024 p out = (p in - 2560)*32 + 4096 p out = (p in - 3456)*64 + 32768 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 10000 20000 30000 40000 50000 60000 70000 12-bit code output 16-bit code input
ar0331_ds rev. l pub. 5/15 en 27 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor high dynamic range mode as described in table 8, the ar0331 companding block operates on 16-bit input only. for the exposure ratios that do not result in 16-bit s, bit shifting occurs before the data enters the companding block. as a result of the bit shift, data needs to be unshifted after linear- ization in order to obtain the proper imag e. table 9 provides the bit operation that should occur to the data after linearization. hdr-specific exposure settings in hdr mode, pixel values are stored in line buffers while waiting for both exposures to be available for final pixel data combination. there are 70 line buffers used to store inter- mediate t1 data. due to this limitation, th e maximum coarse integration time possible for a given exposure ratio is equal to 70*t1/t2 lines. for example, if r0x3082[3:2] = 2, the sensor is set to have t1/t2 ratio = 16x. therefore the maximum number of integration lines is 70*16 = 1120 lines. if coarse integration time is greater than this, the t2 integration time will stay at 70. the sensor will calculate the ratio internally, enabling the li nearization to be performed. if companding is being used, then relinearization would still follow the programmed ratio. for example if the t1/t2 ratio was programmed to 16x but coarse in tegration was increased beyond 1120 then one would still use the 16x relinearization formulas. an additional limitation is the maximum numb er of exposure lines in relation to the frame_length_lines register. in linear mode, maximum coarse_integration_time = frame_length_lines - 1. however in hdr mode, since the coarse integration time register controls t1, the max coarse integratio n time is frame_length_lines - 71. putting the two criteria listed above together, the formula is as follows: (eq 2) there is a limitation of the minimum number of exposure lines, which is one row time for linear mode. in hdr mode, the minimum number of rows required is half of the ratio t1/t2. table 8: knee points for compression from 16 bits to 12 bits t1/t2 exposure ratio (r1) r0x3082[3:2] p1 p ou t1 = p1 p2 p out 2= (p2 - p1)/2 + 1024 p3 p out 3= (p3 - p2)/32 + 2560 pmax p out max = (pmax - p3)/64 +3456 4x, 8x, 16x, 32x 2 10 1024 2 12 2560 2 15 3456 2 16 3968 table 9: bit operation after linearization ratio_t1_t2 (r0x3082[3:2])/ ratio_t1_t2_cb (r0x3084[3:2]) bit shift operation after linearization 4x right shift 2 bits 8x right shift 1 bit 16x no shift 32x left shift 1 bit maximum coarse_integration_time minimum 70 t1 t2, frame_length_lines 71 ? ? ? ?? =
ar0331_ds rev. l pub. 5/15 en 28 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor reset motion compensation in typical multi-exposure hdr systems, moti on artifacts can be created when objects move during the t1 or t2 integration time. when this happens, edge artifacts can poten- tially be visible and might l ook like a ghosting effect. to correct this, the ar0331 has special 2d motion compensation circuitry that detects motion artifacts and corrects the image. the motion compensation feature can be enab led by setting r0x318c[14] = 1. additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. for more information, refer to the ar0331 register reference document and the ar0331 developer guide. reset the ar0331 may be reset by the reset_bar pin (active low) or the reset register. hard reset of logic the reset_bar pin can be connected to an external rc circuit for simplicity. the recommended rc circuit uses a 10k ? resistor and a 0.1 ? f capacitor. the rise time for the rc circuit is 1 ? s maximum. soft reset of logic soft reset of logic is controlled by the r0x301a reset register. bit 0 is used to reset the digital logic of the sensor. furthermore, by as serting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. this bi t is a self-resetting bit and also returns to ?0? during two-wire serial interface reads. sensor pll vco figure 20: pll dividers affecting vco frequency the sensor contains a phase-locked loop (pll ) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre-pll clock divider followed by a multiplier. the pll multiplier should be an even integer. if an odd integer (m) is programmed, the pll will defaul t to the lower (m-1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for th e sensor array, the pixel anal og and digital readout paths, and the output parallel and serial interfaces . use of the pll is required when using the hispi interface. extclk (6-48 mhz) pre_pll_clk_div 2 (1-64) pll_multiplier 58 (32-384) f vco
ar0331_ds rev. l pub. 5/15 en 29 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor pll dual readout paths there are two readout paths within the sensor digital block. the sensor pll should be configured such that the total pixel rate acro ss both readout paths is equal to the output pixel rate. for example, if clk_pix is 74.25 mhz in a 4-lane hispi configuration, the clk_op should be equal to 37.125 mhz. figure 21: sensor dual readout paths the sensor row timing calculation refers to each data-path individually. for example, the sensor default configuration uses 1100 clocks per row (lin e_length_pck) to output 1928 active pixels per row. the aggregate clocks per row seen by the receiver will be 2200 clocks (1100 x 2 readout paths). parallel pll configuration figure 22: pll for the parallel interface . the maximum output of the parallel interface is 74.25 mpixel/s. this will limit the readout clock (clk_pix) to 37.125 mpixel /s. the sensor will not use the f serial , f seri- al_clk , or clk_op when configured to use the parallel interface. pixel array all digital blocks all digital blocks serial output (hispi) clk_pix clk_pix pixel rate = 2 x clk_pix = # data lanes x clk_op (hispi) = clk_op (parallel) extclk (6-48 mhz) f vco pre_pll_clk_div 2(1-64) pll_multiplier 58(32 - 384) vt_sys_clk_div 1 (1,2,4,6,8,10 12,14,160 vt_pix_clk_div 6(4-16) clk_op (max 74.25 mp/s) clk_pix (max 37.125 mp/s)
ar0331_ds rev. l pub. 5/15 en 30 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor pll serial pll configuration figure 23: pll for the serial interface the pll must be enabled when hispi mode is selected. the sensor will use op_sys_- clk_div and op_pix_clk_div to configure the output clock per lane (clk_op). the config- uration will depend on the number of active lanes (1, 2, or 4) configured. to configure the sensor protocol and number of lanes, refer to ?serial configuration? on page 22. table 10: pll parameters for the parallel interface parameter symbol min max unit external clock extclk 6 48 mhz vco clock f vco 384 768 mhz readout clock clk_pix 37.125 mpixel/s output clock clk_op 74.25 mpixel/s table 11: example pll configuration for the parallel interface parameter value output f vco 445.5 mhz (max) vt_sys_clk_div 1 vt_pix_clk_div 6 clk_pix 37.125 mpixel/s (= 445.5mhz / 12) clk_op 74.25 mpixel/s (= 445.5mhz / 6) output pixel rate 74.25 mpixel/s pre_pll _clk_div 2 (1-64) pll _ multiplier 58 (32 ? 384) vt_sys_clk_div 1 (1,2,4,6,8, 10,12,14,16) vt_pix_clk_div 6 (4-16) op_sys_clk_div (default = 1) op_pix_clk_div 12 (8,10,12) f serial f vco f vco clk_pix clk_op
ar0331_ds rev. l pub. 5/15 en 31 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor pll configure the serial output so that it adheres to the following rules: ? the maximum data-rate per lane (f serial ) is 700 mbps/lane (hispi). ? configure the output pixel rate per lane (clk_op) so that the sensor output pixel rate matches the peak pixel rate (2 x clk_pix). ? 4-lane: 4 x clk_op = 2 x clk_pix = pixel rate (max: 148.5 mpixel/s) ? 2-lane: 2 x clk_op = 2 x clk_pix = pixel rate (max: 74.25 mpixel/s) ? 1-lane: 1 x clk_op = 2 x clk_pix = pixel rate (max: 37.125 mpixel/s) stream/standby control the sensor supports a soft standby mode. in this mode, the external clock can be option- ally disabled to further minimize power cons umption. if this is done, then the ?power- up sequence? on page 62 must be followed. when the external clock is disabled, the sensor will be unresponsive to re gister writes and other operations. soft standby is a low-power st ate that is controlled thro ugh register r0x301a[2]. the sensor will go to standby after completion of the current frame readout. when the sensor comes back from soft standby, previously written register settings are still main- tained. soft standby will not occur if the trigger pin is held high. a specific sequence needs to be followed to enter and exit from soft standby. entering soft standby: 1. set r0x301a[12] = 1 if serial mode was used 2. set r0x301a[2] = 0 and drive trigger pin low. table 12: pll parameters for the serial interface parameter symbol min max unit external clock extclk 6 48 mhz vco clock f vco 384 768 mhz readout clock clk_pix 74.25 mpixel/s output clock clk_op 37.125 mpixel/s output serial data rate per lane f serial 300 (hispi) 700 (hispi) mbps output serial clock speed per lane f serial_clk 150 (hispi) 350(hispi) mhz table 13: example pll configurations for the serial interface parameter 4-lane 2-lane 1-lane units 16-bit 14-bit 12-bit 10-bit 12-bit 10-bit 10-bit f vco 594 519.75 445.5 742.5 445.5 742.5 742.5 mhz vt_sys_clk_div 1 1 1 2 1 2 4 vt_pix_clk_div 8 7 6 5 12 10 10 op_sys_clk_div 1 1 1 2 1 2 2 op_pix_clk_div 16 14 12 10 12 10 10 f serial 594 519.75 445.5 371.25 445.5 371.25 371.25 mhz f serial_clk 297 259.875 222.75 185.63 222.75 185.63 185.63 mhz clk_pix 74.25 74.25 74.25 74.25 37.125 37.125 18.563 mpixel/s clk_op 37.125 37.125 37.125 37.125 37.125 37.125 37.125 mpixel/s pixel rate 148.5 148.5 148.5 148.5 74.25 74.25 37.125 mpixel/s
ar0331_ds rev. l pub. 5/15 en 32 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor readout 3. turn off external clock to further minimize power consumption exiting soft standby: 1. enable external clock if it was turned off 2. set r0x301a[2] = 1 or drive trigger pin high. 3. set r0x301a[12] = 0 if serial mode is used sensor readout image acquisition modes the ar0331 supports two image acquisition modes: ? electronic rolling shutter (ers) mode this is the normal mode of operation. wh en the ar0331 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic wi thin the sensor sequen ces through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. when the integration time is changed (by using th e two-wire serial interface to change regis- ter settings), the timing and control logic co ntrols the transition from old to new inte- gration time in such a way that the stream of output frames from the ar0331 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the ar0331 register refer- ence. ? global reset mode this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration ti me is controlled by an external electro- mechanical shutter, and the ar0331 provides control signals to interface to that shut- ter. the benefit of using an external electromechani cal shutter is that it eliminates the visual artifacts associated with ers operation. visu al artifacts arise in ers operation, particu- larly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is contro lled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. readout modes horizontal mirror when the horiz_mirror bit (r0x3040[14]) is se t in the read_mode register, the order of pixel readout within a row is revers ed, so that readout starts from x_addr_end + 1 and ends at x_addr_start . figure 24 on page 33 shows a sequence of 6 pixels being read out with r0x3040[14] = 0 and r0x3040[14] = 1.
ar0331_ds rev. l pub. 5/15 en 33 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor readout figure 24: effect of horizontal mirror on readout order vertical flip when the vert_flip bit (r0x3040[15]) is set in the read_mode register, the order in which pixel rows are read out is reversed , so that row readout starts from y_addr_end and ends at y_addr_start . figure 30 shows a sequence of 6 rows being read out with r0x3040[15] = 0 and r0x3040[15] = 1. figure 25: effect of vertical flip on readout order g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] g3[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] line_valid horiz_mirror = 0 d out [11:0] horiz_mirror = 1 d out [11:0] row0[11:0] row1[11:0] row2[11:0] row3[11:0] row4[11:0] row5[11:0] row6[11:0] row5[11:0] row4[11:0] row3[11:0] row1[11:0] frame_valid vert_flip = 0 d out [11:0] vert_flip = 1 d out [11:0] row2[11:0]
ar0331_ds rev. l pub. 5/15 en 34 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor subsampling subsampling the ar0331 supports subsamplin g. subsampling allows the se nsor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. the following examples are configured to use either 2x2 or 3x3 subsampling. figure ? 26: ?? horizontal ? binning ? in ? the ? ar0331 ? sensor horizontal binning is achieved either in th e pixel readout or the digital readout. the sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. figure ? 27: ?? vertical ? row ? binning ? in ? the ? ar0331 ? sensor vertical row binning is applied in the pixel re adout. row binning can be configured as 2x or 3x rows within the same color plane. pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. skipping pixels in the x-direction will not re duce the row time. skipping pixels in the y- direction will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifact s from aliasing. refer to the ar0331 devel- oper guide for details on configuring skipping, binning, and summing modes for color and monochrome operation. lsb lsb lsb lsb - lsb lsb e - e - e - e -
ar0331_ds rev. l pub. 5/15 en 35 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor frame rate sensor frame rate the time required to read out an image frame (t frame ) can be derived from the number of clocks required to output each image and the pixel clock. the frame-rate is the inverse of the frame period. fps=1/t frame (eq 3) the number of clocks can be simplified further into the following parameters: ? the number of clocks required for each sensor row ( line_length_pck ) this parameter also determines the sensor row period when referenced to the sensor readout clock. (t row = line_length_pck x 1/clk_pix) ? the number of row periods per frame ( frame_length_lines ) ? an extra delay between frames used to achieve a specific output frame period ( extra_delay ) t frame =1/(clk_pix) [frame_length_lines li ne_length_pck + extra_delay] (eq 4) figure 28: frame period measured in clocks frame_length_lines = active rows + vb
ar0331_ds rev. l pub. 5/15 en 36 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor sensor frame rate row period (t row ) line_length_pck will determine the number of clock periods per row and the row period (t row ) when combined with the sensor readout clock. line_length_pck includes both the active pixels and the horizontal blanking time per row. the sensor utilizes two readout paths, as seen in figure 21 on page 29 , allowing the sensor to output two pixels during each pixel clock. the minimum line_length_pck is defined as the maximum of the following three equa- tions: adc readout limitation: (eq 5) digital readout limitation: (eq 6) output interface limitations: (eq 7) row periods per frame frame_length_lines determines the number of row periods (t row ) per frame. this includes both the active and blanking rows . the minimum vertical blanking value is defined by the number of ob rows read per frame, two embedded data rows, and two blank rows. a minimum number of idle rows equal to the t2 integration time should be added in hdr mode to allow for changes in in tegration time by an auto exposure algo- rithm. for example, if the coarse integration time is 320 lines and the exposure ratio is 16x, then the minimum vertical blanking would be 8 + 2 + 2 + 20 = 32 rows. the minimum (default) number of idle rows is 4. (eq 8) the sensor is configured to output frame information in two embedded data rows by setting r0x3064[8] to 1 (default). if r0x3064[8] is set to 0, the sensor will instead output two blank rows. the data configured in the two embedded rows is defined in ?embedded data and statistics? on page 45. notes: 1. min_vertical_blanking includes the default number (4) of idle rows. table 14: minimum vertical blanking configuration r0x3180[7:4] ob rows min_vertical_blanking 1 0x8 (default) 8 ob rows 8 ob + 8 = 16 0x4 4 ob rows 4 ob + 8 = 12 0x2 2 ob rows 2 ob + 8 = 10 line_length_pck 1100 ? 1 3 -- - x_addr_end x_addr_start 1 + ? x_odd_inc 1 + ?? 0.5 ? -------------------- --------------------- ------------------ --------------- - ? 1 2 -- - x_addr_end x_addr_start ?1 + x_odd_inc 1 + ?? 0.5 ? -------------------- --------------------- ------------------ ---------------- 96 + ? minimum frame_length_lines y_addr_end y_addr_start ?1 + y_odd_inc 1 + ?? 2 ? --------------------- --------------------- ------------------ --------------- min_vertical_blanking + =
ar0331_ds rev. l pub. 5/15 en 37 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor slave mode the locations of the ob rows, embedded rows, and blank rows within the frame readout are identified in figure 29: ?slave mode ac tive state and vertical blanking,? on page 37. slave mode the slave mode feature of the ar0331 supports triggering the start of a frame readout from a vd signal that is suppl ied from an external asic. the slave mode signal allows for precise control of frame rate and register chan ge updates. the vd signal is an edge trig- gered input to the trigger pin and must be at least 3 pi xclk cycles wide. figure 29: slave mode active state and vertical blanking if the slave mode is disabled, the new frame will begin after the extra delay period is finished. the slave mode will react to the rising edge of the input vd signal if it is in an active state. when the vd signal is received, the sensor will begin the frame readout and the slave mode will remain inactive for the period of one frame time plus 16 clock periods (t frame + (16 / clk_pix)). after this period, the slave mode will re-enter the active state and will respond to the vd signal. start of frame n end of frame n start of frame n + 1 time frame valid ob rows (2, 4, or 8 rows) embedded data row (2 rows) active data rows blank rows (2 rows) extra vertical blanking (frame_length_lines - min_frame_length_lines) vd signal slave mode active state the period between the rising edge of the vd signal and the slave mode ready state is t frame + 16 clocks. extra delay (clocks)
ar0331_ds rev. l pub. 5/15 en 38 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor slave mode figure 30: slave mode example with eq ual integration and fr ame readout periods the integration of the last row is started before th e end of the programmed integration for the first row. the row shutter and read operations will stop when the slave mode becomes active and is waiting for the vd signal. the following should be considered when configuring the sensor to use the slave mode: 1. the frame period (t frame ) should be configured to be less than the period of the input vd signal. the sensor will disregard the input vd signal if it appears before the frame readout is finished. 2. if the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input vd signal. this error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between vd signals). inactive active row 0 row n inactive active rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger rising edge of vd signal triggers the start of the frame readout. row reset (start of integration) frame valid vd signal rising edge the slave mode will become active after the last row period. both the row reset and row read operations will wait until the rising edge of the vd signal.. row reset and read operations begin after the rising edge of the vd signal.
ar0331_ds rev. l pub. 5/15 en 39 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor slave mode figure 31: slave mode example where the integrat ion period is half of the frame readout period the sensor read pointer will have paused at row 0 while th e shutter pointer pauses at row n/2. the extra integration caused by the slave mode delay will only be seen by rows 0 to n/2. the example below is for a frame readout period of 16.6ms while the integration ti me is configured to 8.33ms. when the slave mode becomes active, the sensor will pause both row read and row reset operations. (note: the row integration period is defined as the period from row reset to row read.) the frame-time should therefore be configured so that the slave mode ?wait period? is as short as possible. in the case where the sensor integration time is shorter than the frame time, the ?wait period? will only increase the integration of the rows that have been reset following the last vd pulse. the period between slave mode pulses must also be greater than the frame period. if the rising edge of the vd pulse arrives while the slave mode is inactive, the vd pulse will be ignored and will wait until the next vd pulse has arrived. to e nte r s lave mo de : 1. while in soft-standby, set r0x30ce[4] = 1 to enter slave mode. 2. enable the input pins (trigger) by setting r0x301a[8] = 1. 3. enable streaming by setting r0x301a[2] = 1. 4. apply sync-pulses to the trigger input. inactive active row 0 row n inactive active rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger row reset (start of integration) frame valid vd signal rising edge reset operation is held during slave mode active state. row reset and read operations begin after the rising edge of the vd signal. 8.33 ms 8.33 ms
ar0331_ds rev. l pub. 5/15 en 40 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor frame readout frame readout the sensor readout begins with vertical blanking rows foll owed by the active rows. the frame readout period can be defined by th e number of row periods within a frame ( frame_length_lines ) and the row period ( line_length_pck/clk_pix ). the sensor will read the first vertical blanking row at the beginning of the frame pe riod and the last active row at the end of the row period. figure 32: example of the sensor output of a 1928 x 1088 frame at 60 fps the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming-sp protocol. figure 32 aligns the frame integration and read out operation to the sensor output. it also shows the sensor output using the hispi stre aming-sp protocol. different sensor proto- cols will list different sync codes. table 15: serial sync codes included with each protocol included with the ar0331 sensor interface/protocol start of vertical blanking row (sov) start of frame (sof) start of active line (sol) end of line (eol) end of frame (eof) parallel parallel interface uses frame valid (fv) and line va lid (lv) outputs to denote start and end of line and frame. hispi streaming-s required unsupport ed required unsupported unsupported hispi streaming-sp required required required unsupported unsupported hispi packetized sp unsupported r equired required required required active rows vertical blanking time 1/60s end of frame readout end of frame readout start of vertical blanking start of frame start of active row end of line serial sync codes end of frame row reset row read row reset row read frame valid line valid 1/60s row reset row read row reset row read 1928 x 1088 1928 x 1088 hb (136 pixels/column) hb (136pixels/column) vb (37 rows) vb (37 rows)
ar0331_ds rev. l pub. 5/15 en 41 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor frame readout figure 33 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1125 vb rows were added to the output frame to reduce the 1928 x1088 frame rate from 60 fps to 30 fp s without increasing the delay between the readout of the first an d last active row. figure 33: example of the sensor output of a 1928 x1088 frame at 30 fps the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming-sp protocol. serial sync codes vb (37 rows) h b (1236 p ixels ) h b (1236 p ixels ) frame valid line valid 1/30s 1/30s active rows vertical blanking time end of frame readout start of vertical blanking start of frame start of active row end of line end of frame row reset row read row reset row read 1928 x 1088 1928 x 1088 row reset row read row reset row read end of frame readout vb (37 rows)
ar0331_ds rev. l pub. 5/15 en 42 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes changing sensor modes register changes all register writes are delayed by one frame. a register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2 . this includes writes to the sensor gain and integration registers. real-time context switching in the ar0331, the user may switch between two full register sets a and b by writing to a context switch change bit in r0x30b0[13]. wh en the context switch is configured to context a the sensor will reference the cont ext a registers. if the context switch is changed from a to b during the readout of frame n , the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2 . the sensor will show the same behavior when changing from context b to context a. table 16: list of configurable registers for context a and context b context a context b register description address register description address coarse_integration_time 0x3012 coa rse_integration_time_cb 0x3016 line_length_pck 0x300c line_length_pck_cb 0x303e frame_length_lines 0x300a fr ame_length_lines_cb 0x30aa row_bin 0x3040[12] row_bin_cb 0x3040[10] col_bin 0x3040[13] col_bin_cb 0x3040[11] fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8] coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12] x_addr_start 0x3004 x_addr_start_cb 0x308a y_addr_start 0x3002 y_addr_start_cb 0x308c x_addr_end 0x3008 x_addr_end_cb 0x308e y_addr_end 0x3006 y_addr_end_cb 0x3090 y_odd_inc 0x30a6 y_odd_inc_cb 0x30a8 x_odd_inc 0x30a2 x_odd_inc_cb 0x30ae green1_gain 0x3056 green1_gain_cb 0x30bc blue_gain 0x3058 blue_gain_cb 0x30be red_gain 0x305a red_gain_cb 0x30c0 green2_gain 0x305c green2_gain_cb 0x30c2 global_gain 0x305e g lobal_gain_cb 0x30c4 operation_mode_ctrl 0x3082 operation_mode_ctrl_cb 0x3084 bypass_pix_comb 0x318e[13:12] bypass_pix_comb_cb 0x318e[15:14]
ar0331_ds rev. l pub. 5/15 en 43 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes figure 34: example of changing th e sensor from context a to context b combi mode to facilitate faster switching between linear and hdr modes, the ar0331 includes a combi mode feature. when enabled, comb i mode loads a single (hdr) sequencer. when switching from hdr to linear modes, the sequencer remains the same, but only the t1 image is output. while not optimized fo r linear mode operation, it allows faster mode switching as a new sequencer load is not needed. combi mode is enabled by setting bit r0x30ba[8]. see the ar0331 developer guide for more information on combi mode. compression when the ar0331 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using a-la w compression. the compression is applied after the data pedestal has been added to the data. see ?pedestals? on page 25. the a-law compression is disabled by default and can be enabled by setting r0x31d0 from ?0? to ?1?. table 17: a-law compression table for 12-10 bits input range input values compressed codeword 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g x 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g x x 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h x x 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h x x x 1 1 a b c d e f g h active rows vertical blanking time 1/60s 1/60s start of vertical blanking start of frame start of active row end of frame serial sync codes c end of frame readout end of frame readout end of frame readout 1/30s 1928x1088 frame n+1 1928x1088 frame n vb (37 rows) h b (136 p ixels /c olum n ) vb (37 rows) hb (136 pixels/column) 2048x1536 frame n+2 vb (37 rows) hb (76 p ixels/column) ) write context a to b during readout of frame n integration time of context b mode implemented during readout of frame n+1 context b mode is implemented in frame n+2
ar0331_ds rev. l pub. 5/15 en 44 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes temperature sensor the ar0331 sensor has a built-in ptat-based temperature sensor, accessible through registers, that is capable of me asuring die junction temperature. the temperature sensor can be enabled by writing r0x30b4[0]=1 and r0x30b4[4]=1. after this, the temperature sensor output value can be read from r0x30b2[9:0]. the value read out from the temperature sens or register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device characteristic response is qu ite linear in the temperature range of oper- ation required, a simple linear function in th e format of the equation below can be used to convert the adc output value to the final temperature in degrees celsius. (eq 9) for this conversion, a minimum of two known points are needed to construct the line formula by identifying the slope and y-intercept ?t 0 ?. these calibration values can be read from registers r0x30c6 and r0x30c8, which correspond to value read at 70 c and 55 c respectively. once read, the slope and y- intercept values can be calculated and used in equation 9. for more information on the temperature sens or registers, refer to the ar0331 register reference. temperature slope r0x30b2 9:0 ?? t + ? 0 =
ar0331_ds rev. l pub. 5/15 en 45 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes embedded data and statistics the ar0331 has the capability to output imag e data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout. ?embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ? embedded statistics: if enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. figure 35: frame format with embedded data lines enabled embedded data the embedded data contains the configurat ion of the image being displayed. this includes all register settings used to capture the current frame. the registers embedded in these rows are as follows: line 1: registers r0x3000 to r0x312f line 2: registers r0x3136 to r0x31bf, r0x31d0 to r0x31ff note: all undefined registers will have a value of 0. the format of the embedded register data transmission is defined per the embedded data section of the smia function specification. in parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8 msb and 8 lsb. the alignment of the 8-bit data will be on the 8 msb bits of the 12-bit pixel word. for example, if a register value of 0x1234 is to be transmitted, it will be transmitted over two, 12-bit pixels as follows: 0x120, 0x340. image register data status & statistics data hblank vblank
ar0331_ds rev. l pub. 5/15 en 46 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes embedded statistics the embedded statistics cont ain frame identifiers and hi stogram information of the image in the frame. this can be used by do wnstream auto-exposure algorithm blocks to make decisions about exposure adjustment. this histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 2 8 , 120 evenly spaced bins for values 2 8 to 2 12 , 60 evenly spaced bins for values 2 12 to 2 16 . in hdr with a 16x exposure ratio, this approximately corre- sponds to the t1 and t2 exposures respectively. the statistics found in line 2 are for backwards compatibility. it is recommended that auto exposure algorithms be devel- oped using the histogram statistics on line 1. the first pixel of each line in the embedded statistics is a tag value of 0x0b0. this signi- fies that all subsequent statistics data is 10 bit data aligned to the msb of the 12-bit pixel. figure 36 summarizes how the embedded statistics transmission looks like. it should be noted that data, as shown in figure 36, is aligned to the msb of each word: figure 36: format of embedded st atistics output within a frame the statistics embedded in these rows are as follows: line 1: ? 0x0b0 - identifier ? register 0x303a - frame_count ? register 0x31d2 - frame id ? histogram data - histogram bins 0-243 line 2: ?0x0b0 (tag) ?mean ?histogram begin ?histogram end ?low end histogram mean ? percentage of pixels below low end mean ? normal absolute deviation {2'b00,frame _count msb} {2'b00,frame _count lsb} {2'b00,frame _id msb} {2'b00,frame _id lsb} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin1 [19:0] histogram bin1 [9:0] # words = 10'h1ec data_format_ code = 8'h0b histogram bin243 [19:0] histogram bin243 [9:0] # words = 10'h00c data_format_ code = 8'h0b mean [19:10] mean [9:0] histbegin [19:10] histbegin [9:0] histend [19:10] histend [9:0] lowendmean [19:10] lowendmean [9:0] perc_lowend [19:10] perc_lowend [9:0] norm_abs_ dev [19:10] norm_abs_ dev [9:0] 8'h07 8'h07 8'h07 stats line 1 stats line 2
ar0331_ds rev. l pub. 5/15 en 47 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor changing sensor modes test patterns the ar0331 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r0x3070). only one of the test patterns can be enabled at a given point in time by sett ing the test_pattern_mode register according to table 18. when test patterns are enabled th e active area will receive the value speci- fied by the selected test pattern and the dark pixels will receive the value in test_pat- tern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_red (r0x3072) for red pixels. solid color when the color field mode is selected, the value for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is select ed, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1s mode is selected, a wa lking 1s pattern will be sent through the digital pipeline. the first value in each row is 1. table 18: test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color test pattern 2 100% vertical color bars test pattern 3 fade-to-gray vertical co lor bars test pattern 256 walking 1s test pattern (12-bit)
ar0331_ds rev. l pub. 5/15 en 48 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the ar0331.the interface protoc ol uses a master/slave model in which a master controls one or more slave devices. th e sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive s clk low; the ar0331 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high.
ar0331: 1/3-inch 3.1 mp/full hd digital image sensor two-wire serial register interface ar0331_ds rev. l pub. 5/15 en 49 ?semiconductor components industries, llc, 2015. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ar0331 are 0x20 (write address) and 0x21 (read address) in accordance with the specificatio n. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. an alternate slave address can al so be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transf er. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s intern al register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0331: 1/3-inch 3.1 mp/full hd digital image sensor two-wire serial register interface ar0331_ds rev. l pub. 5/15 en 50 ?semiconductor components industries, llc, 2015. single read from random location this sequence (figure 37) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 37 shows how the internal register address maintained by the ar0331 is loaded and incremented as the sequence proceeds. figure 37: single read from random location single read from current location this sequence (figure 38) performs a read using the current value of the ar0331 internal register address. the master terminates th e read by generating a no-acknowledge bit followed by a stop condition. the figure shows two independent read sequences. figure 38: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+ 1 a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a
ar0331_ds rev. l pub. 5/15 en 51 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 39) starts in the same way as the single read from random loca- tion (figure 37). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 39: sequential read, start from random location sequential read, start from current location this sequence (figure 40) starts in the same way as the single read from current loca- tion (figure 38). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 40: sequential read, start from current location single write to random location this sequence (figure 41) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 41: single write to random location slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+1 a a write data
ar0331_ds rev. l pub. 5/15 en 52 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 42) starts in the same way as the single write to random location (figure 41). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the writ e is terminated by the master generating a st op condition. figure 42: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
ar0331_ds rev. l pub. 5/15 en 53 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor spectral characteristics spectral characteristics figure 43: quantum efficiency 0 5 10 15 20 25 30 35 40 45 50 55 60 65 350 450 550 650 750 850 950 1050 1150 quantum efficiency (%) wavelength (nm) red green blue
ar0331_ds rev. l pub. 5/15 en 54 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications electrical specifications unless otherwise stated, the following spec ifications apply under the following condi- tions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +85 c; output load = 10pf; frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 44 and table 19. figure 44: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 19: two-wire seri al bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications ar0331_ds rev. l pub. 5/15 en 55 ?semiconductor components industries, llc, 2015. notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automa tically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the ar0331 launches pixel data, fv, and lv with the rising edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the falling edge of pixclk. see figure 45 below and table 20 on page 56 for i/o timing (ac) characteristics. figure 45: i/o timing diagram serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? table 19: two-wire serial bu s characteristics (continued) f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max data[11:0] line_valid/ frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. pixclk *pll disabled for t cp extclk t cp t r t extclk t f t plh t pfh t pfl t pll t pd t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% rp fp 90% 10% frame_valid
ar0331_ds rev. l pub. 5/15 en 56 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications note: i/o timing characteristics are me asured under the following conditions: - temperature is 25c ambient - 10pf load table 20: i/o timing characteristics symbol definition condition min typ max unit f extclk1 input clock frequency 6 C 48 mhz t extclk1 input clock period 20.8 C 166 ns t r input clock rise time C 3 C ns t f input clock fall time C 3 C ns t rp pixclk rise time C 4 C ns t fp pixclk fall time C 4 C ns clock duty cycle 40 50 60 % t (pix jitter) jitter on pixclk C 1 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled C11.3C ns f pixclk pixclk frequency default, nominal voltages 674.25mhz t pd pixclk to data valid default, nominal voltages C2.3C ns t pfh pixclk to fv high default, nominal voltages C1.5C ns t plh pixclk to lv high default, nominal voltages C2.3C ns t pfl pixclk to fv low default, nominal voltages C1.5C ns t pll pixclk to lv low default, nominal voltages C2C ns c load output load capacitance C <10 C pf c in input pin capacitance C 2.5 C pf
ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications ar0331_ds rev. l pub. 5/15 en 57 ?semiconductor components industries, llc, 2015. dc electrical characteristics the dc electrical characteristics are shown in the tables below. caution stresses greater than those listed in table 14 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. note: exposure to absolute maximum rating condit ions for extended periods may affect reliability. table 21: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage vdd_io*0.7 C C v v il input low voltage C C vdd_io*0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage vdd_io-0.3 C C v v ol output low voltage C C 0.4 v i oh output high current at specified v oh -22 C C ma i ol output low current at specified v ol CC22ma table 22: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 2.4 v v dd _io_max i/o digital voltage C0.3 4 v v aa _max analog voltage C0.3 4 v v aa _pix pixel supply voltage C0.3 4 v v dd _pll pll supply voltage C0.3 4 v vdd_slvs_max hispi i/o digital voltage C0.3 2.4 v t st storage temperature C40 85 c
ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications ar0331_ds rev. l pub. 5/15 en 58 ?semiconductor components industries, llc, 2015. notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _pll = 2.8v v dd = v dd _io = 1.8v pll enabled and pixclk = 74.25 mhz t a = 25 c notes: 1. operating currents are measur ed at the following conditions: v aa = v aa _pix = v dd _pll = 2.8v v dd = v dd _io = 1.8v pll enabled and pixclk = 74.25 mhz t a = 25 c table 23: operating current consumption in parallel output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 20 fps i dd 1 C 122 137 ma i/o digital operating current streaming, 2048x1536 20 fps i dd _io C 25 30 ma analog operating current streaming, 2048x1536 20 fps i aa C3238ma pixel supply current streaming, 2048x1536 20 fps i aa _pix C 7 12 ma pll supply current streaming, 2048x1536 20 fps i dd _pll C 8 12 ma digital operating current streaming, 1080p30 i dd 1 C 122 137 ma i/o digital operating current streaming, 1080p30 i dd _io - 25 30 ma analog operating current streaming, 1080p30 i aa C3540ma pixel supply current streaming, 1080p30 i aa _pix C 7 12 ma pll supply current st reaming, 1080p30 i dd _pll C 8 12 ma table 24: operating current consumption in parallel output and hdr mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 20 fps i dd C156173 ma i/o digital operating current streaming, 2048x1536 20 fps i dd _io C 30 35 ma analog operating current streaming, 2048x1536 20 fps i aa C50 65 ma pixel supply current streaming, 2048x1536 20 fps i aa _pix C 9 14 ma pll supply current streaming, 2048x1536 20 fps i dd _pll C 8 12 ma digital operating current streaming, 1080p30 i dd C161184 ma i/o digital operating current streaming, 1080p30 i dd _io C 30 35 ma analog operating curren t streaming, 1080p30 i aa C54 70 ma pixel supply current streaming, 1080p30 i aa _pix C 9 14 ma pll supply current streaming, 1080p30 i dd _pll C 8 12 ma
ar0331_ds rev. l pub. 5/15 en 59 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications notes: 1. operating currents are measur ed at the following conditions: v aa =v aa _pix= v dd _pll=2.8v v dd =v dd _io= 1.8v v dd _slvs = 1.8v pll enabled and pixclk=74.25mhz t a = 25 c notes: 1. operating currents are measur ed at the following conditions: v aa =v aa _pix= v dd _pll=2.8v v dd = v dd _io= 1.8v v dd _slvs = 1.8v pll enabled and pixclk=74.25mhz t a = 25 c table 25: operating current in hispi (hivcm) output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd C252 278 ma analog operating current streaming, 2048x1536 30fps i aa C27 35 ma pixel supply current streaming, 2048x1536 30fps i aa _pix C 5 10 ma pll supply current streaming, 2048x1536 30fps i dd _pll C 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd _slvs C 22 26 ma digital operating current streaming, 1080p60 i dd C276 302 ma analog operating curren t streaming, 1080p60 i aa C37 45 ma pixel supply current streaming, 1080p60 i aa _pix C 7 12 ma pll supply current streaming, 1080p60 i dd _pll C 8 12 ma slvs supply current streaming, 1080p60 i dd _slvs C 22 26 ma table 26: operating current in hispi (hivcm) output and hdr mode definition condition symbol min typ max unit digital operating current s treaming, 2048x1536 30fps i dd C 317 358 ma analog operating current str eaming, 2048x1536 30fps i aa C4555ma pixel supply current streaming, 2048x1536 30fps i aa _pix C 8 13 ma pll supply current streaming, 2048x1536 30fps i dd _pll C 8 12 ma slvs supply current strea ming, 2048x1536 30fps i dd _slvs C 22 26 ma digital operating current streaming, 1080p60 i dd C 323 358 ma analog operating current streaming, 1080p60 i aa C5570ma pixel supply current streaming, 1080p60 i aa _pix C 9 14 ma pll supply current streaming, 1080p60 i dd _pll C 8 12 ma slvs supply current streaming, 1080p60 i dd _slvs C 24 28 ma
ar0331_ds rev. l pub. 5/15 en 60 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications notes: 1. operating currents are measur ed at the following conditions: v aa =v aa _pix= v dd _pll=2.8v v dd =v dd _io= 1.8v v dd _slvs = 0.4v pll enabled and pixclk=74.25mhz t a = 25 c notes: 1. operating currents are measur ed at the following conditions: vaa=vaa_pix= vdd_pll=2.8v vdd = vdd_io= 1.8v vdd_slvs = 0.4v pll enabled and pixclk=74.25mhz ta = 25c table 27: operating current in hispi (slvs) output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd C252 278 ma analog operating current streaming, 2048x1536 30fps i aa C27 35 ma pixel supply current streaming, 2048x1536 30fps i aa _pix C 5 10 ma pll supply current streaming, 2048x1536 30fps i dd _pll C 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd _slvs C 9 13 ma digital operating current streaming, 1080p60 i dd C276 302 ma analog operating curren t streaming, 1080p60 i aa C37 45 ma pixel supply current streaming, 1080p60 i aa _pix C 7 12 ma pll supply current streaming, 1080p60 i dd _pll C 8 12 ma slvs supply current streaming, 1080p60 i dd _slvs C 9 13 ma table 28: operating current in hispi (slvs) output and hdr mode definition condition symbol min typ max unit digital operating current s treaming, 2048x1536 30fps i dd C 317 358 ma analog operating current str eaming, 2048x1536 30fps i aa C4555ma pixel supply current streaming, 2048x1536 30fps i aa _pix C 8 13 ma pll supply current streaming, 2048x1536 30fps i dd _pll C 8 12 ma slvs supply current strea ming, 2048x1536 30fps i dd _slvs C 9 13 ma digital operating current streaming, 1080p60 i dd C 323 358 ma analog operating current streaming, 1080p60 i aa C5570ma pixel supply current streaming, 1080p60 i aa _pix C 9 14 ma pll supply current streaming, 1080p60 i dd _pll C 8 12 ma slvs supply current streaming, 1080p60 i dd _slvs C 9 13 ma
ar0331_ds rev. l pub. 5/15 en 61 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor electrical specifications hispi electrical specifications the on semiconductor ar0331 sensor supports both slvs and hivcm hispi modes. please refer to the high-speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definitions, specif ications, and timing information. the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specifica- tion. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the dll as implemented on ar0331 is limited in the number of available delay steps and differs from the hispi specification as described in this section. note: the clock dll steps 6 and 7 are not reco mmended by on semicond uctor for the ar0331. note: the data dll steps 3, 5, and 7 are not re commended by on semico nductor for the ar0331. table 29: channel skew measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; data rate =480 mbps; dll set to 0 data lane skew in reference to clock tchskew1phy -150 ps table 30: clock dll steps measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; data dll set to 0 clock dll step 1 2 3 4 5 step delay at 660 mbps 0.25 0.375 0.5 0.625 0.75 ui eye_opening at 660 mbps 0.85 0.78 0.71 0.71 0.69 ui table 31: data dll steps measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; clock dll set to 0 data dll step 1 2 4 6 step delay at 660 mbps 0.25 0.375 0.625 0.875 ui eye opening at 660 mbps 0.79 0.84 0.71 0.61 ui
ar0331_ds rev. l pub. 5/15 en 62 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0331 is shown in figure 46. the avail- able power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 100 ? s, turn on v aa and v aa _pix power supply. 3. after 100 ? s, turn on v dd _io power supply. 4. after 100 ? s, turn on vdd power supply. 5. after 100 ? s, turn on vdd_slvs power supply. 6. after the last power supply is stable, enable extclk. 7. assert reset_bar for at least 1ms. the parall el interface will be tri-stated during this time. 8. wait 150000 extclks (for internal initialization into software standby. 9. configure pll, output, and image settings to desired values. 10. wait 1ms for the pll to lock. 11. set streaming mode (r0x301a[2] = 1). figure 46: power up table 32: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix 3 t0 0 100 C ? s v aa /v aa _pix to v dd _io t1 0 100 C ? s v dd _io to v dd t2 0 100 C ? s v dd to v dd _slvs t3 0 100 C ? s xtal settle time tx C 30 1 Cms v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_bar t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
ar0331_ds rev. l pub. 5/15 en 63 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor power-on reset and standby timing notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. hard reset t4 1 2 CC ms internal initialization t5 150000 C C extclks pll lock time t6 1 C C ms table 32: power-up sequence (continued) definition symbol minimum typical maximum unit
ar0331_ds rev. l pub. 5/15 en 64 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor power-on reset and standby timing power-down sequence the recommended power-down sequence for the ar0331 is shown in figure 47. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is acti ve by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 47: power down note: t4 is required between power down and next po wer up time; all decoupling caps from regulators must be completely discharged. table 33: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s pwrdn until next pwrup time t4 100 C C ms v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
ar0331_ds rev. l pub. 5/15 en 65 ?semiconductor components industries, llc, 2015 ar0331: 1/3-inch 3.1 mp/full hd digital image sensor package dimensions package dimensions figure 48: 48 ilcc parallel package outline drawing notes: 1. all dimensions are in millimeters. dimensions in () are for reference only. encapsulant: epoxy substrate material: plastic laminate 0.5 thickness lid material: borosilicate glass 0.4 +- 0.04 thickness. lead finish: gold plating, 0.5 microns minimum thickness. image sensor die: 0.2mm thickness. maximum rotation of optical area relative to package edges: 1 . maximum tilt of optical area relative to substrate plane : 25 ? m. maximum tilt of cover glass relative to optical area plane : 50 ? m. 8. double side ar coating: 420 - 850 nm r < 1% applied to glass. 2 3 4 5 6 7 d e
ar0331_ds rev. l pub. 5/15 en 66 ?semiconductor components industries, llc, 2015 ar0331: 1/3-inch 3.1 mp/full hd digital image sensor package dimensions figure 49: 48 ilcc hispi package outline drawing notes: 1. all dimensions are in millimeters. dimensions in () are for reference only. encapsulant: epoxy substrate material: plastic laminate 0.5 thickness lid material: borosilicate glass 0.4 +- 0.04 thickness. lead finish: gold plating, 0.5 microns minimum thickness. image sensor die: 0.2mm thickness. maximum rotation of optical area relative to package edges: 1 . maximum tilt of optical area relative to substrate plane : 25 ? m. maximum tilt of cover glass relative to optical area plane : 50 ? m. 8. double side ar coating: 420 - 850 nm r < 1% applied to glass. 2 3 4 5 6 7 d e
ar0331_ds rev. l pub. 5/15 en 67 ?semiconductor components industries, llc, 2015 ar0331: 1/3-inch 3.1 mp/full hd digital image sensor package dimensions figure 50: 63-ball ibga package outline drawing notes: 1. all dimensions are in millimeters. dimensions in () are for reference only. encapsulant: epoxy substrate material: plastic laminate 0.25 thickness lid material: borosilicate glass 0.4 +- 0.04 thickness. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to sold er balls post reflow. solder ball is ? 0.5 on a ? 0.4 smd ball pad. image sensor die: 0.2mm thickness. maximum rotation of optical area relative to package edges: 1 . maximum tilt of optical area relative to substrate plane : 25 ? m. maximum tilt of cover glass relative to optical area plane : 50 ? m. 8. double side ar coating: 420 - 850 nm r < 1% applied to glass. 2 3 4 5 6 7 d e
ar0331_ds rev. l pub. 5/15 en 68 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor revision history revision history rev. l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/1/15 ? updated ?ordering information? on page 2 rev. k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/25/15 ? removed confidential marking ? updated format of table of contents rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/19/15 ? updated to on semiconductor template rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/27/14 ? updated figure 1: ?block diagram,? on page 6 ? updated figure 6: ?9.5 x 9.5 mm 63-ball ibga package,? on page 13 ? updated table 3, ?pin descriptions, 9.5 x 9.5 mm, 63-ball ibga,? on page 14 ? updated figure 32: ?example of the sensor output of a 1928 x 1088 frame at 60 fps,? on page 40 ? updated figure 33: ?example of the sensor output of a 1928 x1088 frame at 30 fps,? on page 41 ? updated figure 34: ?example of changing the sensor from context a to context b,? on page 43 ? updated table 33, ?power-down sequence,? on page 64 ? updated figure 48: ?48 ilcc parallel package outline drawing,? on page 65 ? updated figure 49: ?48 ilcc hispi package outline drawing,? on page 66 ? updated figure 50: ?63-ball ibga package outline drawing,? on page 67 ? updated corporate address on last page rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/24/14 ? updated figure 4: ?48 ilcc package, parallel output,? on page 9 ? applied updated aptina template rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/29/12 ? updated figure 6: ?9.5 x 9.5 mm 63-ball ibga package,? on page 13 ? updated ?pixel sensitivity? on page 22 (deleted last sentence in section) ? added table 7, ?companding table,? on page 26 ? updated figure 48: ?48 ilcc parallel package outline drawing,? on page 65 ? updated figure 49: ?48 ilcc hispi package outline drawing,? on page 66 ? updated figure 50: ?63-ball ibga package outline drawing,? on page 67 rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/13/12 ? updated the external reference clock fr equency range from 6-74.25mhz to 6-48mhz (in table 1 and various other locations). ? updated table 3, ?available part numbers,? on page 2 ? updated title of table 3, ?pin descriptions, 9.5 x 9.5 mm, 63-ball ibga,? on page 14 ? changed recommended data pedestal setting from 0 to 16 when altm is enabled (p25) ? removed statement that register values are preserved on a soft reset (p28) ? updated figure 22: ?pll for the parallel interface,? on page 29 ? updated figure 23: ?pll for the serial interface,? on page 30 ? updated table 14, ?minimum vertical blanking configuration,? on page 36
ar0331_ds rev. l pub. 5/15 en 69 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor revision history ? updated the trigger pulse timing for slave mode from t frame - 16 clocks to t frame + 16 clocks (figure 29: ?slave mode active state and vertical blanking,? on page 37). ? updated figure 45: ?i/o timing diagram,? on page 55 ? restored revision history that got deleted from rev. d rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/21/11 ? updated active pixels, hispi supply vo ltage, power consumption, and package options in table 1, ?key parameters,? on page 1 ? updated ?general description? on page 1 ? updated ?general description? on page 6 ? updated ?functional overview? on page 6 ? updated figure 1: ?block diagram,? on page 6 ? added note 7 to figure 3: ?typical configuration: parallel pixel data interface,? on page 8 ?updated v dd _slvs description in table 2, ?pin descriptions, 48 ilcc,? on page 12 ? changed titles of figure 6: ?9.5 x 9.5 mm 63-ball ibga package,? on page 13 and table 3, ?pin descriptions, 9.5 x 9.5 mm, 63-ball ibga,? on page 14 ?updated v dd _slvs description in table 3, ?pin descriptions, 9.5 x 9.5 mm, 63-ball ibga,? on page 14 ? updated ?pixel array structure? on page 16 ? added note 1 to figure 7: ?pixel array description,? on page 16 ? updated table 4, ?output enable control,? on page 18 ? updated ??parallel interface? on page 18? ? updated ?dll timing adjustment? on page 20 ? updated figure 12: ?block diagram of dll timing adjustment,? on page 20 ? updated ?hispi protocol layer? on page 21 ? updated ?serial configuration? on page 22 ? added ?pixel sensitivity? heading before figure 15: ?integration control in ers readout,? on page 22 ? updated ?gain stages? on page 23 ? updated figure 15: ?integration control in ers readout,? on page 22 ? deleted ?positional gain adjustments (pga) on page 18? ? updated table 6, ?recommended sensor gain,? on page 24 ? removed ?table 9, ?recommended registers to configure sensor gain table? on page 24 ? updated ?pedestals? on page 25 ? updated ?high dynamic range mode? on page 25 ? updated ?adaptive local tone mapping? on page 25 ? updated ?companding? on page 26 ? updated ?hdr-specific expo sure settings? on page 27 ? removed ?clocks? on page 28 ? updated ?vco? on page 28 ? removed figure 17: ?row read and row reset showing fine integration? on page 23 ? removed equation 3 on page 23 ? updated ?dual readout paths? on page 29 ? updated ?parallel pll co nfiguration? on page 29 ? updated ?serial pll configuration? on page 30 ? updated figure 23: ?pll for the serial interface,? on page 30
ar0331_ds rev. l pub. 5/15 en 70 ?semiconductor components industries, llc, 2015. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor revision history ? updated table 12, ?pll parameters for the serial interface,? on page 31 ? added 14-bit column to 4-lane section in table 13, ?example pll configurations for the serial interface,? on page 31 ? updated ?stream/standby control? on page 31 ? updated ?image acquisition modes? on page 32 ? updated ?horizontal mirror? on page 32 ? updated ?subsampling? on page 34 ?updated ?row period (t row )? on page 36 ? updated ?row periods per frame? on page 36 ? updated ?slave mode? on page 37 ? updated note for table 14, ?minimum vert ical blanking configuration,? on page 36 ? updated ?combi mode? on page 43 ? updated ?temperature sensor? on page 44 ? updated ?embedded statistics? on page 46 ? added note to table 20, ?i/o ti ming characteristics,? on page 56 ? updated ?hispi electrical specifications? on page 61 ? updated table 23, ?operating current cons umption in parallel output and linear mode,? on page 58 ? updated table 24, ?operating current co nsumption in parall el output and hdr mode,? on page 58 ? updated table 25, ?operating current in hispi (hivcm) output and linear mode,? on page 59 ? updated table 26, ?operating current in hispi (hivcm) output and hdr mode,? on page 59 ? added table 27, ?operating current in hisp i (slvs) output and linear mode,? on page 60 ? added table 28, ?operating current in hi spi (slvs) output and hdr mode,? on page 60 ? updated note for table 30, ?clock dll steps,? on page 61 ? updated note for table 31, ?data dll steps,? on page 61 ? updated ?power-up sequence? on page 62 ? added note to pin 48 of figure 48: ?48 ilcc parallel package outline drawing,? on page 65 ? added figure 49: ?48 ilcc hispi package outline drawing,? on page 66 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/8/11 ? updated ?features? on page 1 ? updated table 3, ?available part numbers,? on page 2 ? updated table 5, ?configuration of the pixel data interface,? on page 18 ? updated ?gain stages? on page 23 ? updated table 6, ?recommended sensor gain,? on page 24 ? changed title of ?data pedestals? to ?pedestals? on page 25 and updated ? updated ?vco? on page 28 ? updated table 13, ?example pll configurat ions for the serial interface,? on page 31 ? updated ?horizontal mirror? on page 32 ? updated ?vertical flip? on page 33 ? updated ?slave mode? on page 37
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. ar0331: 1/3-inch 3.1 mp/full hd digital image sensor revision history ar0331_ds rev. l pub. 5/15 en 71 ?semiconductor components industries, llc, 2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. ? updated table 15, ?serial sync codes included with each protocol included with the ar0331 sensor,? on page 40 ? added ?combi mode? on page 43 ? added ?spectral characteristics? on page 53 ? updated table 23, ?operating current cons umption in parallel output and linear mode,? on page 58 ? updated table 24, ?operating current co nsumption in parall el output and hdr mode,? on page 58 ? updated table 25, ?operating current in hispi (hivcm) output and linear mode,? on page 59 ? updated table 26, ?operating current in hispi (hivcm) output and hdr mode,? on page 59 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/8/11 ? updated ?features? on page 1 ? updated figure 2: ?typical configuratio n: serial four-lane hispi interface,? on page 7 ? updated figure 3: ?typical configuration: parallel pixel data interface,? on page 8 ? updated table 3, ?available part numbers,? on page 2 ? updated table 1, ?pin descriptions,? on page 10 ? updated table 2, ?pin descriptions, 48 ilcc,? on page 12 ? updated table 3, ?pin descriptions, 9.5 x 9.5 mm, 63-ball ibga,? on page 14 ? added ?pixel output interfaces? on page 18 ? added ?the correction function? on page 18 ? updated ?serial configuration? on page 22 ? updated table 6, ?recommended sensor gain,? on page 24 ? updated table 8, ?knee points for compression from 16 bits to 12 bits,? on page 27 ? added table 9, ?bit operation after lineariz ation,? on page 27 with introductory text above it ? updated table 20, ?i/o timing characteristics,? on page 56 ? updated figure 48: ?48 ilcc parallel package outline drawing,? on page 65 ? updated figure 50: ?63-ball ibga package outline drawing,? on page 67 ? updated corporate address on last page rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/26/11 ?initial release

▲Up To Search▲

Price & Availability of AR0331SRSC00SHCAH-GEVB

	To Download AR0331SRSC00SHCAH-GEVB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .